Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis.According to this criterion,three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics.Experimental data showed that,as the second snapback voltage decreased from 25.4 to 8.1 V,the discharge ability of the optimized structure increased from 0.57 to 3.1 A.
参考文献
| [1] | Ker M D,Lin K H.Double snapback characteristics in highvoltage nMOSFETs and the impact to on-chip ESD protection design.IEEE Electron Device Lett,2004,25(9):640 |
| [2] | Knaipp M,Park J M,Vescoli V.Evolution of a CMOS based lateral high voltage technology concept.Microelectron J,2006,37(3):243 |
| [3] | Sun W F,Shi L X,Sun Z L,et al.High-voltage power IC technology with nVDMOS,RESURF pLDMOS,and novel level-shift circuit for PDP scan-driver IC.IEEE Trans Electron Devices,2006,53(4):891 |
| [4] | Lai T H,Ker M D,Chang W J,et al.High-robust ESD protection structure with embedded SCR in high-voltage CMOS process.Reliability Physics Symp,2008:627 |
| [5] | Chang W J,Ker M D.The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology.IEEE Trans Device Mater Reliab,2007,7(2):324 |
| [6] | Linten D,Vashchenko V,Scholz M,et al.Extreme voltage and current overshoots in HV snapback devices during HBM ESD stress.Proc EOS/ESD Symp,2008:204 |
上一张
下一张
上一张
下一张
计量
- 下载量()
- 访问量()
文章评分
- 您的评分：
-
10%
-
20%
-
30%
-
40%
-
50%