参考文献
| [1] | Qian Q,Sun W,Zhu J,et al.Investigation of the shift of hot spot in lateral diffused LDMOS under ESD conditions.Microelectron Reliab,2010,50:1935 |
| [2] | Mergens M P J,Wilkening W,Mettler S,et al.Analysis of lateral DMOS power devices under ESD stress conditions.Electron Devices,2000,47:2128 |
| [3] | Moens P,Van den bosch G.Characterization of total safe operating area of lateral DMOS transistors.Device Mater Reliab,2006,6:349 |
| [4] | Lai T,Ker M,Chang W,et al.High-robust ESD protection structure with embedded SCR in high-voltage CMOS process.IRPS,2008:627 |
| [5] | Imoto T,Mawatari K,Wakiyama K,et al.A novel ESD protection device structure for HV-MOS ICs.IEEE Intemational Reliability Physics Symposium,2009:663 |
| [6] | Lee J,Su H,Chan C,et al.The influence of the layout on the ESD performance of HV-LDMOS.ICSICT,2010:303 |
| [7] | Chen W,Ker M,Jou Y,et al.Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection.ISCAS,2009:385 |
| [8] | Lin L,Jiang L,Fan H,et al.Impact of parasitic resistance on the ESD robustness of high-voltage devices.Journal of Semiconductors,2012,33(1):59 |
| [9] | Ker M,Hsu H.The impact of inner pickup on ESD robustness of multi-finger NMOS in nanoscale CMOS technology.IEEE International Reliability Physics Symposium,2006:631 |
| [10] | Murrmann H,Widmann D.Current crowding on metal contacts to planar devices.Electron Devices,1969,12:1022 |
| [11] | Wu D,Jiang L,Fan H,et al.Analysis on the positive dependence of channel length on ESD failure current ofa GGNMOS in a 5 V CMOS.Journal of Semiconductors,2013,34(2):024004 |
| [12] | Yang Z,Liu H,Wang S.A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process.Journal of Semiconductors,2013,34(4):045010 |
| [13] | Voldman S H.Latchup.Chichester,England:John Wiley and Sons,Ltd,2007:125 |
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