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[1] Salman A,Gauthier R,Stadler W,et al.NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology.IEEE Trans Device Mater Reliab,2002,12(1):2
[2] Oh K H,Banerjeel K,Duvwg C,et al.Non-uniform conduction induced reverse channel length dependence of ESD reliability for silicided NMOS transistors.IEEE IEDM,2002:341
[3] Pogany D,Johnsson D,Bychikhin S,et al.Measuring holding voltage related to homogeneous current flow in wide ESD protection structures using multilevel TLP.IEEE Trans Electron Devices,2011,58(2):411
[4] Dong S,Du X,Han Y,et al.Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications.IEEE Electron Lett,2008,44(19):1129
[5] Lee J H,Wu K M,Huang S C,et al.The dynamic current distribution of a multi-fingered GGNMOS under high current stress and HBMESD events.IEEE Reliab Phys Symp Proc,2006:629
[6] Chen T Y,Ker M D.Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process.IEEE Trans Semicond Manufacturing,2003,16(3):486
[7] Bock K,Russ C,Badenes G,et al.Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology.IEEE Trans Components,Packaging,and Manufactory Technology-Part C,1998,21(4):286
[8] Bock K,Keppens B,De Heyn V,et al.Influence of gate length on ESD-performance for deep submicron CMOS technology.EOS/ESD Symposium,1999:95
[9] Sze S M.Physics of semiconductor devices.3rd ed.New York:Wiley,2007:257
[10] Chen X B,Zhang Q Z.Theory and design of transistors.2nd ed.Beijing:Publishing House of Electronics Industry,2008:132 (in Chinese)
[11] Li M Z,Wei G P,Chen X B.Analysis of local electro-thermal effects of LDM OS power device.Chinese Journal of Semiconductors,2005,26(9):1823
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