研究了Pb3O4对(Co,Nb)掺杂SnO2压敏材料电学性质的影响.当Pb3O4的含量从0.00增加到0.75%(摩尔分数,下同)时,(Co,Nb)掺杂SnO2压敏电阻的击穿电压从426 V/mm迅速减小到160 V/mm,40 Hz时的相对介电常数从1240迅速增加到2760.这说明Pb3O4是调控SnO2压敏材料击穿电压和介电常数的敏感添加剂.晶界势垒高度测量表明,在实验范围内Pb的含量对势垒高度的影响很小.随着Pb含量的增加,SnO2的晶粒尺寸的迅速长大是击穿电压迅速减小和介电常数迅速增大的主要原因.对样品的复阻抗进行了测量,发现未掺杂Pb的样品具有最低的晶界电阻,而掺杂0.50%Pb3O4的样品具有最高的晶界电阻.提出了一个修正的缺陷势垒模型,指出了替代Sn的受主不应当处于晶界上,而应处于耗尽层的Sn的晶格位置.
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