TFT-LCD驱动芯片中需要较大容量的内置存储器,相对于静态存储电路而言,动态存储电路节省了芯片的面积,有利于芯片成本的降低.文章讨论了用于TFT-LCD驱动芯片内置DRAM的分块设计方法,结合芯片物理特点将其分为左右对称两块.采用改进的3-T结构DRAM存储阵列,省去了伪存储单元,节省了面积,降低了功耗.优化了DRAM的刷新电路,省略了判断信号与RAS和CAS先后顺序的仲裁电路.结合芯片本身的特点设计了行、列译码电路.对于芯片的仿真,采用了模拟验证和形式验证相结合的前端设计验证方法,同时又采用了结构化抽取寄生参数和建立关键路径的后仿真.
参考文献
[1] | Chang Mutien,Huang Po-Tsang,Wei H W.A 65 nm low power 2T1D embeeded DRAM with leakage current reduction[J].IEEE International SOC Conference,2007,26-29:207-210. |
[2] | Segawa Yuuichi.Refresh circuit for DRAM with three-transistor type memory cells:US,5812476[P].1998-09-22. |
[3] | Bruce Jacob,Spencer W Ng,Wang David T.Memory Systems Cache DRAM Disk[M].US:Elsevier Inc,2008. |
[4] | Lazar P S.DRAM with total self refresh and control:US,6741515[P].2004-05-25. |
[5] | Anadn D,Coivno J,Dreibelbis J.A 1.0 GHz multi-banked embedded DRAM in 65 nm CMOS featuring concurrent refresh and hierarchical BIST[J].IEEE Custom Integrated Circuits Conference,2007,16-19:795-798. |
[6] | Karandikar A,Parhi K K.Low power SRAM design using hierarchical divided bit-line approach[C]//International Conference on Computer Design,Austin:IEEE,1998:82-89. |
[7] | Kaku M,Iwai H,Nagai T.An 833MHz pseudo-two-port embedded DRAM for graphics applications[J].IEEE International Solid-State Circuits Conference,2008,(3-7):276-613. |
[8] | 梁茂,魏廷存,魏晓敏,等.单片集成TFT-LCD驱动芯片内置SRAM验证技术研究[J].液晶与显示,2008,23(1):91-95. |
[9] | 张锋,周玉梅,黄令仪.一种用于SRAM的快速仿真模型[J].半导体学报,2005,26(6):1264-1268. |
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