为降低某线阵CCD相机因屡次调试而被损坏的风险,对相机的特性和时序进行了分析,设计了一种基于现场可编程门阵列(FPGA)的CCD相机模拟器.整个系统以FPGA作为核心器件,在FPGA内部开辟一片ROM,里面存放一幅标准图像的灰度值,在像素时钟的下降沿输出灰度值,并对像素时钟进行计数,产生外加行同步信号和行有效信号.仿真结果显示,此线阵CCD相机模拟器模拟过程符合实际相机的输出时序要求.模拟器的设计缩短了工程上的调试时间,为后期的采集和存储等处理提供了保证.
In order to reducing the damaged risk of a linearity CCD camera which was debug frequently, the CCD camera's characteristic and timing diagram were analyzed, a CCD camera simulation system was designed based on Field Programmable Gate Array(FPGA). The system made the FPGA as the core device, a Read Only Memory(ROM) was in inaugurated inside FPGA, which stored a standard image gray data, output gray data in the falling edge of pixel clock, counted the amount of pixel clock which bringed Trigger Line Readout and horizontal synchronization signal. The simulation results show the simulation process of the linearity CCD camera simulation system satisfies the demand of CCD camera timing diagram. The design of the simulation system shortens the engineering debug time, provides guarantee for evening data collection and storage.
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