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重点介绍器件进入纳米尺度后出现的 MOSFET/SOI器件的新结构,如超薄 SOI器件、双栅 MOSFET、 FinFET和应变沟道等 SOI器件,并对它们的性能进行了分析.

参考文献

[1] International Technology Roadmap for semiconductor SIA[M].,2001
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[4] Kevin Teixeira .Intal's Terahertz Transistor Architecture[EB/OL].http://www.intel com/research/silicon/spotlights/terahertzbkgdr htm,2002.
[5] Gerald Marcyk;Robert Chau .New Transistor for 2005 andBeyond[EB/OL].www.intelcom/research/silicon/terahertzlongpdf,2003.
[6] Robert Chau;Tack Kavalieros;Brain Doyle et al.A 50nmdepleted-ubstrate CMOS transistor (DST)[EB/OL].http://www.intel com/research/silicon/DST paper pdf,2003.
[7] Lochtefeld A;Meinhold M;Langdo T .CMOS Technology for 25nm Channel Length[EB/OL].http://www.-tlmitedu/mtlhome/6Res/AR2002/03_elec/002_cmostetfnmchlepdf
[8] Jvi-song Lin;Shih-hangChang.Recessed Multi-ate SOI MOSFET in deep decanonometer Regime[A].:47-48.
[9] Ritenour A;Lauer I .Self-ligned Double-ate CMOS Technology for 3- integration[EB/OL].http://www.tlmitedu/mtlhome/6Res/AR2000BED/EDabs3pdf,2002.
[10] Xue-ue Huang;Wen-hin Lee;Charles Kuo .Sub-50nm P-hannel FinFET[J].IEEE Transactions on Electron Devices,2001,48(05):880-886.
[11] Stephen H Tang;Leland Chang;Nick Lindert et al.FinFET- Quasi-lanar double-ate MOSFET ISSCC2001/SESSION 7/Technology directions: AdvancedTechnologies/7 4[EB/OL].http://www-evice eccs berkeley edu/~ leland/publications/isscco pdf,2003.
[12] Michael I Current;Shari N Farrens.Atomic-ayerCleaving with SixGey strain layers for fabrication of Si and Ge-ich SOI devices layers[A].:11-12.
[13] Yee Chia yeo;Vivek Subramanian;Jakub Kedzierski et al.Nanoscale ultra-hin-ody silicon-n- insulator p-MOSFET with a SiGe/Si heterostructure channel[J].IEEE Transactions on Electron Devices,2000,21(04):161-163.
[14] Wong H S P .Beyond the conventional transistor[EB/OL].http://www.research ibm com/journal/rd/462/wong html,2003.
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