本文研究了部分耗尽绝缘体上的硅(PDSOI)NMOS、CMOS结构的闩锁(latch)特性.提出了一种体电极触发诱发PDSOI NMOS器件闩锁效应维持电压的测试方法,并用此方法测试出了不同栅长、栅宽和体接触结构NMOS/CMOS的闩锁效应维持电压,以及沟道注入条件和温度对维持电压的影响.
The partially depleted SOI (PDSOI) NMOSFET and CMOSFETs latch characteristics are stud-ied in this paper. A holding voltage measure method by bulk electrode trigger PDSOI NMOSFET latch effect is proposed. We use this method measured out the holding voltage of NMOSFET/CMOSFET tran-sistors with different gate width, gate length, bulk contact types, and the influence of the channel im-plantation condition and temperature.
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